A Novel and Efficient Approach for RC Delay Evaluation of On-chip VLSI Interconnect under Current Mode Signaling Technique
نویسندگان
چکیده
Current-mode signaling significantly increases the bandwidth of on-chip interconnects compared to voltage mode signaling and reduces the overall propagation delay. A delay formula for current mode is necessary for estimation of delay and bandwidth for VLSI systems. In this paper, closed-form expression of delay model based on the effective lumped element resistance and capacitance approximation of distributed RC lines are presented. A new closed-form solution of delay under step input excitation is developed. The usefulness of this solution is that both resistive and capacitive load termination is accurately modeled for use in current mode signaling. Comparison of simulation results with other established models justifies the accuracy of our approach.
منابع مشابه
High Speed Energy Efficient Signal Transmission On Global VLSI Interconnect
Article history: Received: September 15, 2010 Revised: October 10, 2010 Available online :Nov. 06, 2010 This paper suggests high speed and energy efficient current mode (CM) signaling technique for on chip data transmission. The system comprises of driver and receiver with decoding circuit. It is shown that CM signaling technique improves the delay parameter thrice compare to voltage mode signa...
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